Process for manufacturing semiconductor device

ABSTRACT

In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.

TECHNICAL FIELD

The present invention relates to a method of manufacturing asemiconductor apparatus, and more particularly, to a method ofmanufacturing a semiconductor apparatus which intends to improve a yieldof the semiconductor apparatus by improving a test process.

A conventional semiconductor apparatus has been manufactured inaccordance with the following processes.

Device forming process for forming a multiplicity of devices on a wafer.

Probing test process for applying a probing test (a continuity test) toa multiplicity of devices formed on the wafer (a subject to be tested)

Dicing process for dicing the wafer (cutting the wafer at everyintegrated circuits) after the probing test process is finished so as toform a plurality of chips.

Package process for packaging each of the chips as a semiconductorapparatus

Burn-in test process for applying a burn-in test (a thermal load test)to the semiconductor apparatus (a subject to be tested).

In this case, among the processes mentioned above, the subject to betested in the probing test and the burn-in test, an external test systemand a connecting method are basically the same. That is, there isemployed a method of mechanically contacting each of conductive fineprobes with each of electrode pads patterned on the subject to be testat a pitch of about some tens to a hundred and some tens μm, having alength and a width of some tens to a hundred and some tens μm and athickness of about 1 μm and made of an aluminum alloy or the otheralloys. As the fine probe, for example, there is employed a narrow probemade of a tungsten (W) or a nickel (Ni) and having a diameter of a tipof some tens μm and a length of some tens mm.

DISCLOSURE OF THE INVENTION

However, in the probe structure in accordance with the prior artmentioned above, a large area is required for accurately positioningeach of the probes so as to fix. Accordingly, it is hard to arrange moreprobes within the surface, so that a number of the electrode pads and anumber of the chips which can be tested at one time have been limited.

Then, techniques for solving the problems mentioned above are disclosed,for example, in Japanese Patent Unexamined Publication No. 1-147374,Japanese Patent Unexamined Publication No. 9-148389, Japanese PatentUnexamined Publication No. 9-243663 and the like.

In Japanese Patent Unexamined Publication No. 1-147374, the structure ismade such that a plurality of beam structures are formed on a single Sisingle crystal flat plate in a direction of a main plane, a projectionis formed in each of tips thereof, and a conductor layer is formed in adirection of a fixed end of the beam structure from the projection.

In Japanese Patent Unexamined Publication No. 9-148389, the structure ismade such that Si substrate having three layers formed in differentshapes are laminated, a piezoelectric component is arranged on thelowermost layer near a plurality of beam structures and the fixed end ofeach of the beam structures, and conducting means for conducting the tipof the beam structure with an open surface on the uppermost layer isprovided.

In Japanese Patent Unexamined Publication No. 9-243663, an elastomer isinterposed between a Si substrate having an aggregate of projectionsconducting with an external portion and a fixed plate.

However, in Japanese Patent Unexamined Publication No. 1-147374, since aterminal end (an electrode) of a wire within the Si substrate is alwaysformed on substantially the same surface as a probe (projection) formingsurface within the Si substrate, there is a problem that the subject tobe tested is interfered when performing an electric connection forwardfrom the electrode.

Further, in Japanese Patent Unexamined Publication No. 9-148389, sinceit is necessary to provide the piezoelectric component in the middle ofthe beam structure, there is a great problem in view of a cost and ayield in the case of forming a multiplicity of probes.

Still further, in Japanese Patent Unexamined Publication No. 9-243663,the elastomer is directly provided on the back surface of the Sisubstrate in the structure of the test structure, however, a throughgroove is always formed in the periphery of each of the beams in thecase that the beam structure is provided, so that there is a possibilitythat it flows out to a side of the subject to be tested due to apressure at a time of pressing. Further, there is a possibility that theSi substrate weakened by an etching due to a lot of load necessary at atime of testing the subject to be tested in a lump is broken.

An object of the present invention is to make it possible to test anelectrode pad of a wafer in a large area and in a lump, in an electriccharacteristic testing process corresponding to a process ofsemiconductor apparatus manufacturing processes.

In order to achieve the object mentioned above, in accordance with thepresent invention, there is provided a method of manufacturing asemiconductor apparatus comprising:

a device forming process for forming a multiplicity of devices on awafer;

a probing test process for applying a probing test to the wafer (asubject to be tested) on which the multiplicity of devices are formed;and

a burn-in test process for applying a burn-in test to the wafer 8 (asubject to be tested) on which the multiplicity of devices are formed,or chip thereof

wherein the structure is made as follows.

(1) In the probing test process and/or the burn-in test process, aconductive projection is provided on a main surface, and there isincluded a process for pressing the projection of a test structure inwhich the projection and a pad provided on a surface opposite to themain surface are electrically connected to a desired position of thesubject to be tested.

(2) In the item (1), the test structure is provided with a conductiveprojection on a main surface, and there are provided a first platemember in which the projection and the pad provided on the surfaceopposite to the main surface are electrically connected, a second platemember arranged on the side of a surface forming the pad of the firstplate member and in which the pad and a wire formed on the second platemember are electrically connected, and a third plate member arrangedbetween the first plate member and the second plate member, formed by amaterial having a Young's modulus of 60 GPa or more and having athickness of 100 μm or more.

(3) In the item (2), a number of test conductor portions existing withina projection surface of the first plate member to the wafer or chip in astate of pressing said projections to a desired position of said waferor chip and a number of the projections formed in the first plate memberformed in an electrically independent manner are equal to each other.

(4) In the item (2) or (3), a plurality of the projections are presentand a through groove crossing over a straight line connecting adjacenttwo projections is provided in the first plate member.

(5) In any one of the items (2) to (4), a space is present between theprojection and the third plate member.

(6) In any one of the items (1) to (5), a plurality of the first platemembers are provided within a substantially the same plane.

(7) In any one of the items (1) to (6), a part other than the projectionof the first plate member or all the area and the subject to be testedare in contact when pressing the projection at a desired position of thesubject to be tested.

The inventors of the present application have searched a known art onthe basis of the result of the present invention. As a result, JapanesePatent Unexamined Publication No. 5-243344, Japanese Patent UnexaminedPublication No. 6-123746, Japanese Patent Unexamined Publication No.7-7052 and Japanese Patent Unexamined Publication No. 8-148553 arelisted up. However, none of them describes the present invention asmentioned below.

In Japanese Patent Unexamined Publication No. 5-243344, there isdisclosed a structure in which a plurality of metal projections areformed on a thin and flexible thin film, that is, a membrane by using aplating technology and the like and each of them is formed as a probe,in order to make it possible to obtain a denser probe arrangement.However, since each of the probes is arranged and formed by newly pilingup a plating on the surface of the flat membrane or attaching aconductive projection, a dispersion tends to be generated in a height ofeach of the probes, so that it is hard to bring a multiplicity of probesinto the electrode pad of the subject to be tested in a lump. Further,in the probe formed by the method of piling up the plating, a shape ofthe surface of the projection is substantially formed in a sphericalsurface shape in many cases and a large surface is going to be broughtinto contact with the subject to be tested, so that a great load isrequired for the purpose that one projection and the electrode pad areconductive. Further, in the method of forming the plating within aplating mold previously formed at a high accuracy and having a sharp tipshape and forming an accurate projection obtained by removing theplating mold as a probe, a dispersion of an initial height can bereduced, however, a plastic deformation is easily generated since a loadis concentrated in the sharpened tip portion. Accordingly, the shape ofthe tip is blunted due to a repeated use and it is hard to use for along time. As a result, it is necessary to frequently replace the probe,so that a test cost is increased.

In Japanese Patent Unexamined Publication No. 6-123746, there isdisclosed a structure in which a notch is formed in a base material (acard) by setting a synthetic resin and a metal as a base material so asto form a probe which can elastically deforms independently. However,since the base material for forming the probe is a synthetic resin and ametal, there is a great difference of coefficient of thermal expansionwith respect to Si corresponding to the material of the subject to betested. Accordingly, when forming the probe corresponding to the largesubject to be tested such as all the area of the wafer or the like,there is a disadvantage that a position shift is generated in an innerdirection on the base material and the wafer surface due to atemperature variation for a testing environment. Further, in the case offorming the present structure by a synthetic resin, since a generalminimum working size is greater than an electrode pad forming rule forthe subject to be tested, it is hard to form the structure itself incorrespondence to the subject to be tested. In addition, in order thateach of the probes is conductive with the electrode pad, it is necessaryto apply a predetermined load in accordance with a shape of the probe, amaterial and the like, however, since a low elastic body such as asynthetic resin does not have a rigidity capable of generating the load,it is hard to conduct. For example, even when the load can be generatedby designing a size of the formed notch and the like, it can be obtainedas a result of applying an excessive tensile strain to the syntheticresin. Accordingly, a permanent strain is generated in the syntheticresin after one pressing, so that a desired load can not be generated atthe later pressing time. Further, it is not actual to form the basematerial by a metal since it is hard to form the notch itself incorrespondence to the electrode pad forming rule for the subject to betested.

In Japanese Patent Unexamined Publication No. 7-7052, there is discloseda structure in which a plurality of structures constituted by beams,projections and metal skin films are formed by setting Si or a metal asa base material so as to form each of the projections as a probe.However, in accordance with this method, since in the projection at aportion near a center of the Si substrate, that is, at a portion apartfrom an outer side surface of the Si substrate, it is necessary to forma wire to an outer peripheral side surface of the Si substrate withkeeping away from the projection at the portion nearer the outer sidesurface of the Si substrate and the following wire, in the case that amultiplicity of projections are formed, lengths of the wires incorrespondence to the respective projections are not aligned as well asa layout for wiring becomes hard, so that there is a disadvantage thatit is impossible to obtain a wire impedance matching necessary formeasuring an electric characteristic.

In Japanese Patent Unexamined Publication No. 8-148553, there isdisclosed a structure in which a wire is provided by setting Si as abase material and an anisotoropic conducting film as a probe and thewire is communicated with a back surface of the base material from athrough hole. However, since a testing substrate made of Si and a wafercorresponding to the subject to be tested are electrically connected byusing the anisotoropic conducting film having a relatively highresistance in place of the plating as the probe, at first, it isnecessary to apply a great pressing load in order to perform an electricconnection at a resistance equal to or less than a necessarypredetermined value. Next, when applying the great pressing load asmentioned above to a finely working probe corresponding to a size of theelectrode pad of the subject to be tested, a conductor (in many cases, ametal powder) within the anisotoropic conducting film escapes in adirection perpendicular to a pressing direction, so that the resistanceis further increased. As a result, there is a disadvantage that a stableelectric connection can not be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross sectional view of a structure of a testingbody in accordance with an embodiment of the present invention;

FIG. 2 is a schematic view of a structure of a testing body inaccordance with another embodiment of the present invention;

FIG. 3 is a schematic view of a structure of a testing body inaccordance with the other embodiment of the present invention;

FIG. 4 is a schematic view of a structure of a testing body inaccordance with further the other embodiment of the present invention;

FIG. 5 is a schematic view of a structure of a testing body inaccordance with further the other embodiment of the present invention;

FIG. 6 is a schematic view of a structure of a testing body inaccordance with further the other embodiment of the present invention;

FIG. 7 is a schematic view of a structure of a testing body inaccordance with further the other embodiment of the present invention;

FIG. 8 is a schematic view of an outer appearance of a wafer inaccordance with an embodiment of the present invention;

FIG. 9 is a schematic view of an outer appearance of a wafer inaccordance with an embodiment of the present invention;

FIG. 10 is a schematic exploded view which shows a part of a main bodyportion of a test system used in a probing test process in accordancewith an embodiment of the present invention;

FIG. 11 is a schematic perspective view of a first plate member inaccordance with an embodiment of the present invention as seen from asurface opposite to a projection forming surface; and

FIG. 12 is a partially detailed view of a first plate member inaccordance with an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment in accordance with the present invention willbe described below with reference to the accompanying drawings.

FIG. 10 is a schematic exploded view which shows a part of a main bodyportion of a test system used in a probing test process in accordancewith the present invention. In the present test system, there areinstalled a heating apparatus for heating a wafer 2 to be tested and avacuum adsorption apparatus for fixing the wafer 2, and there isprovided a wafer stage 100 having a drive mechanism for controlling arelative distance between the wafer and a test structure. The wafer ismounted and fixed on the wafer stage 100 so that surfaces opposite tothe tested surface are faced, and is normally heated and controlled at atemperature of about 90 to 120° C. The test structure is attached to anupper portion of the wafer in a vertical direction by mechanicallyfixing a second plate member 6 to the present test system. At this time,as a matter of course, the test structure is directed so that a firstplate member 1 is directly faced to the tested wafer. In this case, thefirst plate member 1 and the second plate member 6 are mechanicallyintegrated by a predetermined method in detail described below beforebeing attached to the test system.

The first plate member 1 is formed by setting Si having an outerdiameter substantially equal to or more than that of the wafer 2 as abase material. This is because of the purpose for making it possible toform a probe corresponding to positions of all electrode pads to betested within all area of the wafer, as a result it makes it possible topress, that is, test all the wafer in a lump.

The present probing test process is performed by relatively approachingand contacting both of the wafer and the test structure and pressingthem until a predetermined pressing amount after positioning the waferfixed to the test system and the test structure with respect to thecorresponding electrode pad and projection.

With respect to the wafer 2 after finishing the probing test process inthis manner, it is judged by a tester whether good or bad an LSI circuitconduction is at every chips among them. The results thereof are used asa data for judging whether or not a conduction correction at each of thechips is required, whether or not it is necessary to apply apredetermined load to each of the chips in a next burn-in process andwhether or not it is necessary to return a result of the burn-inprocess.

In this case, a method of manufacturing a semiconductor apparatus inaccordance with the present embodiment includes the following processes.

Device forming process for forming a multiplicity of devices on a wafer.

Probing test process for applying a probing test (a continuity test) toa wafer on which a plurality of devices are formed.

Burn-in test process for applying a burn-in test (a thermal load test)to the wafer on which a plurality of devices are formed or chip thereof.

Hereinafter, each of the processes will be in detail described below.

[Device Forming Process]

The device formation is performed with respect to the wafer in which asurface thereof is mirror finished after slicing a single crystal Siingot thin through a multiplicity of unit processes at everyspecification of devices to be manufactured. A detailed descriptionthereof will be omitted, however, for example, in the case of a popularC-MOS (Complementary Metal Oxide Semiconductor), it is formed afterpassing through a P-type and N-type wafer substrate forming process, adevice separating process, a gate forming process, a source/drainforming process, a wiring process, a protective film forming process andthe like, in a rough classification.

Here, in this state, the wafer mentioned above shows an outer appearanceshown in FIGS. 8 and 9. A size of one of chips 21 formed within thewafer 2 is set, for example, such that a line thereof is about some mmto some tens mm, and some tens to some hundreds of electrode pads 211are provided in each of them. In this case, a surface of each of theelectrode pads 211 is normally formed in a rectangular shape having aline of some tens μm to a hundred and some tens μm. Further, theprotective film on the surface is uniformly formed on the other circuitportion with avoiding an immediate upper portion of the electrode pad211 at a thickness of normally about some to some tens μm.

The P-type and N-type forming process is structured such as to implant aB or P ion onto the wafer surface and later expand on the surface by adiffusion.

The device separating process is structured such as to form a Si oxidefilm on the surfaced mentioned above, apply a nitriding film patterningfor selecting an area and selectively grow the oxide film in the portionwhich is not patterned, thereby respectively separating into finedevices.

The gate forming process is structured such as to form a gate oxide filmhaving a thickness of some nm between the devices mentioned above,accumulate a poly Si on the upper portion in accordance with a CVD(Chemical Vapor Deposition) method and thereafter work in apredetermined size, thereby forming an electrode.

The source/drain forming process is structured such as to implant an ionof an impurity such as P, B and the like after forming the gateelectrode and form a source/drain diffusion layer by an activatedannealing.

The wiring process is structured such as to pile up Al wire, interlayerinsulating films and the like, thereby electrically connecting each ofthe devices separated in the above process.

The protective film forming process corresponds to a process forpreventing an impurity and a water from entering into the fine deviceformed in the manner mentioned above from the outer portion and reducinga mechanical stress when packaging the circuit later, and is structuredsuch as to form a protective film on the circuit surface.

A wafer has a thickness of some hundreds μm and a diameter of about 4inches to 8 inches, and 200 to 400 circuits are formed on the surfacethrough the processes mentioned above, for example, in the case of DRAM(Dynamic Random Access Memory). A size of a circuit has a line of someto ten and some mm, and some tens to some hundreds of electrode pads areprovided in a circuit. A surface of each of the electrode pads is formedin a rectangular shape having a line of some tens μm.

[Probing Test Process]

This process corresponds to a process for testing a conduction of anelectric signal of each of the devices formed in the device formingprocess, and is normally performed by using the probe apparatus andbringing each of the probes into the electrode pad in the circuit one byone.

[Burn-in Test Process]

This process corresponds to a process for applying a thermal andelectric stress to the circuit so as to select inferiority in anaccelerative manner. The process brings each of the probes into contactwith the electrode pad in the same manner as that of the probing testprocess.

In this case, FIG. 1 is a schematic cross sectional view which shows astructure of a testing body used in the probing test process and theburn-in test process in accordance with the present invention. The firstplate member 1 is structured such as to etch a single Si flat base plateand form a group of projections 11 on the surface facing to the body 2to be tested.

A structure of the first plate member 1 will be in detail describedbelow with reference to FIGS. 11 and 12. FIG. 11 is a schematicperspective view of the first plate member 1 as seen from a surfaceopposite to the projection forming surface. Further, FIG. 12 is apartially enlarged and sectioned schematic perspective view forexplaining each of the components of the first plate also in detail, inwhich FIG. 12A is a view as seen from the same direction as that of FIG.4 and FIG. 12B is a view as seen from the opposite surface. In each ofFIGS. 11, 12A and 12B, in each of the first plate members 1, aweight-shaped projection 11 is formed at a position corresponding to theelectrode pad of the wafer as the body to be tested.

The projection 11 is structured such as to form a conductive coat on aSi core integrated with the first plate obtained by, for example,anisotoropic etching Si in the periphery thereof.

In the tip of the group of the projections 11, a wire pattern 12 forobtaining a conduction between the body 2 to be tested and the outerportion is formed by using a wafer process technique, and the wirepattern 12 is electrically connected to a surface (hereinafter, refer toa back surface) opposite to the surface on which the group ofprojections 11 of the first plate member are formed via a through hole13 provided in the first plate member 1. On the back surface of thefirst plate member 1, the insulating film 3 is provided except a pad 121portion formed in the end portion of the wire pattern 12.

Next, a description will be given of a structure of a test structureusing the first palte member 1 with reference to FIG. 2.

A third plate member 4 is bonded to the back surface of the first platemember 1. The third plate member 4 is used for the purpose of securing aflatness of the first plate member and reinforcing. Accordingly, it isdesirable that it is constituted by a member having a sufficientrigidity capable of achieving the object mentioned above such as Si,AlN, metal, glass and the like and a size. Actually, a member having aYoung's modulus of 60 GPa or more is desirable, and it is constituted bythe member having a thickness of 100 μm or more. An elastomer 5 isprovided on a back surface of the third plate member 4, and a secondplate member 6 is provided on a further back surface thereof. Objects ofthe second plate member 6 are to obtain a conduction between theconductive structure 7 and the external test system, and to provide asufficient rigidity necessary for pressing the test structure.Accordingly, there is generally used a glass epoxy multi-layer printedcircuit board on which multi-layered conductive wires are developed.Further, in the case that it is expected that a whole great bending loadis operated because a number of the probes is great, a load necessaryfor conducting is great, a probe forming area is wide or the like, thematerial may be set to have a rigidity higher than the metal and theceramics. The elastomer 5 is used for the purpose of following thedirection thereof to the body to be tested and reducing a loaddispersion in accordance with a dispersion of a pressing amount betweenthe body to be tested and the first plate member in the case that a mainsurface on which the group of projections 11 of the first plate member 1are formed is relatively inclined with respect to the surface of thebody to be tested. Accordingly, normally, an elastomer having a smallYoung's modulus, for example, showing a rubber elastic motion isemployed. Otherwise, one or a plurality of coil springs or the like maybe provided within the surface. The conductive structure 7 is used forachieving a conduction between the wire pattern 12 and the second platemember 6 in this case. For the conductive structure 7, for example, acontact probe with a fine spring corresponding to an adjacent pitch of1.5 mm or less is used. Further, for the conductive structure 7, aconductive paste in which a metal powder such as a solder ball, Ag(silver) and the like corresponding to the fine pitch of 1.5 mm or lessare mixed may be employed.

Further, for the first plate member 1, there may be employed a structurein which the group of projections 11 and the wire pattern 12 are formedby plating a conductor within an organic plate member surface such as apolyimide and the like in place of Si. An arrow 31 shows an embodimentof a conductive path.

FIG. 2 shows a structure of a first plate member of a testing structurein accordance with another embodiment of the present invention, in whichFIG. 2A is a top elevational view, FIG. 2B is a side elevational viewand FIG. 2C is a bottom elevational view, respectively. In each of thefigures, an area R1 corresponds to an area of a chip among the body tobe tested. Further, an area R2 corresponding to two chips disposed in aleft portion from a center corresponds to one in which a slit 14 passingthrough the first plate member 1 in a thickness direction is formedbetween the adjacent projections 11, as a result, each of theprojections 11 is provided on an independent beam structure, and an areaR3 corresponding to two chips in a right portion corresponds to anexample where they are not provided. In any cases, as is apparent fromFIG. 2B, a back surface of each of the projections 11 is structured suchthat the first plate member 1 is formed thin, for example, by etching,so that a space is formed above the beam structure. In the area R2,since there is the slit, each of the projections 11 can independently bebent at a time of pressing, so that a relative distance with respect tothe corresponding electrode pad at each of the projectionsdiscontinuously changes due to a dispersion of a height of theprojection and the electrode pad or a relative surface incline betweenthe first plate member and the wafer. As a result, even in the case thatan actual pressing amount of each of the projections changes, it ispossible to independently conduct, respectively. The wire pattern 12forms the pad 121 at a position different from a through portion on theback surface of the first plate member 1 after passing through the firstplate member 1 in a thickness direction. When the structure is made inthis manner, it is possible to make a pitch of arrangement of the pad121 greater via a wire pattern 1212 on the back surface even in the casethat the pitch of arrangement of the pad of the body to be tested andthe corresponding projection are very small. When the pitch of thearrangement is enlarged in this manner, an electric connection betweenthe pad 121 and the second plate member by the conductive structure canbe made easy and inexpensive, and it is a necessary countermeasure forkeeping a reliability of connection high. In this case, in accordancewith a certain number of the formed pads, a certain arrangement aspectof the electrode pad of the wafer to be tested and the like, there is acase that the space for arranging the wire pattern 1212 on the backsurface of the first plate member can not secured. In the case mentionedabove, it is necessary to connect the conductive structure 7 on the backsurface of the first plate member by setting the through hole portion asthe pad 121 as it is after adjusting an interval of each of the throughholes by an operation of the wire pattern 12 on the projection formingsurface of the first plate member. FIG. 3 is a cross sectional view of atesting structure structured by employing the first plate member shownin FIG. 2.

FIG. 4 shows a structure of a third plate member of a testing structuredin accordance with further the other embodiment of the presentinvention, in which FIG. 4A is a top elevational view and FIG. 4B is aside elevational view, respectively.

In the present embodiment, as shown in FIG. 4B, a through hole 41 isprovided in the third plate member 4 at a position corresponding to thepad 121 of the first plate member 1, and a wire pattern 42 is providedin a portion from a contact portion with the pad 121 to an upper surfaceof the third plate member 4. The wire pattern 42 constitutes a pad 421at a position different from the through hole 41. Further, theconductive structure 7 connects the pad 421 of the third plate member tothe second plate member 6.

In the present embodiment, since the wire pattern 42 is formed in thethird plate member 4, a structure is made complex in comparison with thepreceding embodiment (FIG. 3). However, in the preceding embodiment(FIG. 3), it is necessary to set the position of the pad brought intocontact with the conductive structure 7 at a position except the beamstructure portion etched thin, on the contrary, in accordance with thepresent embodiment, it is not necessary. Accordingly, even in the casethat the number of the projections 11 is very large, it is possible toarrange them in an easy manner and at a high density due to an operationof an improvement of a redundancy of arranging the pad and animprovement of a freedom of a wire shape.

Further, in this case, it is necessary to connect the conductivestructure to the through hole portion of the third plate member as it isin the case that the space for arranging the wire pattern 42 on the backsurface of the third plate member can not secured due to the number ofthe formed pads, the arrangement aspect of the electrode pad of thewafer to be detected.

FIG. 5 shows a structure of a first plate member of a testing structurein accordance with further the other embodiment of the presentinvention, in which FIG. 5A is a cross sectional view and FIG. 5B is abottom elevational view, respectively.

In accordance with the present embodiment, a plurality of first platemembers 1 are substantially arranged within the same surface. Thisarrangement can be achieved by bonding the first plate members to thesingle third plate member 4 by an adhesive. However, a plurality ofthird plate members 4 may be present in correspondence to an actual sizeand a state of arrangement. This embodiment is employed in the case oftesting a greater area such as a whole surface of the wafer to be testedor the like in a lump. This can be achieved, as mentioned above, byforming all of the conductive path from the pads to be tested andexisting within a plane of projection of one of the first plate memberswithin the first plate member.

In this case, since the conductive path of the pad (not shown) to betested of the body to be tested and existing within the plane ofprojection of the first plate member is structured such that all of themare present within the plane of projection of the first plate memberwithin the first plate member, the object of the present invention canbe achieved.

FIG. 6 shows a state a testing structure in accordance with further theother embodiment of the present invention at a time of testing a body tobe tested, and in particular corresponds to a cross sectional view of aportion near the body to be tested and the projection of the first platemember 1. In the present embodiment, there is shown a state that thefirst plate member 1 brings the back surface into contact with theprotective film 21 of the body 2 to be tested and a difference of heightof a contact position between the back surface of the first plate member1 and the protective film 21 is absorbed by a deflection of the beamportion 15. An aspect of this testing method is important in view ofuniformly controlling an Al film contact pressure of each of theprojections in all around the area of the first plate member 1. That is,because it is possible to relatively cancel a variation of a load on thebasis of a variation of a deflection v in the beam 15 generated due to arelative incline between the main surfaces of the first plate member 1and the body to be tested which is unavoidably generated, an undulationwithin the surfaces of the both, an unevenness, a dispersion of thepressing amount of the body to be tested to the first plate member, bybringing the back surface of the first plate member 1 into contact withthe protective film 21. Accordingly, the load which the projection 11presses the Al film 22 can be controlled t a fixed value due to thedeflection in the beam portion, so that a desired stable load amount canbe always obtained only by making a material and a size of the beamproper. At this time, in the case of using Si for the first plate member1, it is important in view of preventing the beam portion 15 frombreaking to set a tensile stress acting on a lower end portion of thebeam portion 15 to not over about 2 GPa±1 GPa, and further, it isnecessary to set the load acting on the tip of the projection to 1 gf ormore in order to achieve a stable conduction. As a result of anexperiment, it has been known to be effective that the beam sizesatisfying both conditions is set such that a length L is 0.8 to 2 mm, athickness tp is 30 to 50 μm, a width is made in correspondence to aminimum pitch of a layout for the pad 23 of the body to be tested, adeflection v is 15 μm or less and a projection height hp is 20 to 40 μmin order to correspond them. Further, in the case of forming the beamportion with a high accuracy and in a uniform manner, it is possible todesign so as to set the v value nearer the strength of Si, so that onlyin such a case, a shape of the beam portion may be a so-calledcantilever beam. Accordingly, the L value can be reduced at this time,so that there can be obtained an advantage that each of the componentscan be arranged at a higher density.

Working the back surface of each of the projections thinner than theperiphery thereof in the manner of the present embodiment is performedfor the purpose of selectively bending the same portion in the firstplate member at a time of pressing. This is an important countermeasurein view of removing a bad influence to the uniform pressing due to therelative surface incline unavoidably generated between the first platemember and the wafer or a warpage and a deflection of both of themwithout inviting a disadvantage that a significantly great excessiveload in comparison with the pressing load required for the conductioncorresponding to the primary object acts on the projection and theelectrode pad, thereby damaging both of them.

FIG. 7 is a schematic cross sectional view of a testing structure inaccordance with further the other embodiment of the present invention.The present embodiment is structured such that in a state of bringingthe testing structure mentioned in FIG. 5 into contact with a desiredposition of the body to be tested, they are packed by a casing having arigid structure. This shows an aspect for testing a large area in whichthe burn-in test mentioned above is performed, for example, all aroundthe area of the wafer in a lump. Packing in this manner is performed forthe purpose of giving a mobility with accurately pressing, so that it ispossible to apply a burn-in test to a multiplicity of wafers in a lumpby conveying a plurality of the testing structures in this state into anelectric heating furnace in a lump and applying a desired hightemperature state.

In accordance with the present invention, in an electric characteristictesting process corresponding to a process of the semiconductorapparatus manufacturing processes, it is possible to test a large areaof the electrode pad of the body to be tested in a lump.

What is claimed is:
 1. A method of manufacturing a semiconductor apparatus comprising: a device forming process for forming a multiplicity of devices on a wafer; a probing test process for applying a probing test to the wafer (a subject to be tested) on which said multiplicity of devices are formed; and a burn-in test process for applying a burn-in test to the wafer on which said multiplicity of devices are formed or a chip thereof (a subject to be tested), wherein in said probing test process and/or said burn-in test process, a conductive projection is provided on a main surface, and there is included a process for pressing said projection of a test structure in which said projection and a pad provided on a surface opposite to said main surface are electrically connected to a desired position of said subject to be tested, and wherein said main surface is a main surface of a substrate, and said substrate has a first portion and a second portion which is thinner than said first portion, said conductive projection being placed in an area of said second portion, and said second poltion is deformed when pressing said projection.
 2. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein said test structure is provided with a conductive projection on a main surface, and there are provided a first plate member in which said projection and the pad provided on the surface opposite to said main surface are electrically connected, a second plate member arranged on the side of a surface forming said pad of said first plate member and in which said pad and a wire formed on said second plate member are electrically connected, and a third plate member arranged between said first plate member and said second plate member, formed by a material having a Young's modulus of 60 GPa or more and having a thickness of 100 μm or more.
 3. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein a number of test conductor portions existing within a projection surface of said first plate member to said body to be tested in a state of pressing said projections to a desired position of said body to be tested and a number of said projections formed in said first plate member formed in an electrically independent manner are equal to each other.
 4. A method of manufacturing a semiconductor apparatus as claimed in claim 3, wherein a plurality of said projections are present and a through groove crossing over a straight line connecting adjacent two projections is provided in said first plate member.
 5. A method of manufacturing a semiconductor apparatus as claimed in claim 4, wherein, a space is present between said projection and said third plate member.
 6. A method of manufacturing a semiconductor apparatus as claimed in any one of claims 1 to 5, wherein a plurality of said first plate members are provided within a substantially the same plane.
 7. A method of manufacturing a semiconductor apparatus as claimed in claim 6, wherein a part other than the projection of said first plate member or all the area and said subject to be tested are in contact when pressing said projection at a desired position of said subject to be tested.
 8. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein a part other than the projection of said substrate or all the area and said subject to be tested are in contact when pressing said projection at a desired position of said subject to be tested.
 9. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein a plurality of the substrates are provided within a substantially the same plane.
 10. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein, a space is present between said projection and said third plate member.
 11. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein a plurality of said projections are present and a through groove crossing over a straight line connecting adjacent two projections is provided in said first plate member.
 12. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein the substrate is made of silicon.
 13. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein the substrate is made of an organic member.
 14. A method of manufacturing a semiconductor apparatus as claimed in claim 1, wherein said projection and said pad are electrically connected by way of a through hole through said substrate.
 15. A method of manufacturing a semiconductor apparatus as claimed in claim 14, wherein said through hole passes through the substrate at said first portion of the substrate.
 16. A method of manufacturing a semiconductor apparatus comprising: a device forming process for forming a multiplicity of devices on a wafer; a probing test process for applying a probing test to the wafer (a subject to be tested) on which said multiplicity of devices are formed; and a burn-in test process for applying a burn-in test to the wafer on which said multiplicity of devices are formed or a chip thereof(a subject to be tested), wherein in said probing test process and/or said burn-in test process, a conductive projection is provided on a main surface, and there is included a process for pressing said projection of a test structure in which said projection and a pad provided on a surface opposite to said main surface are electrically connected to a desired position of said subject to be tested, wherein said test structure is provided with said conductive projection on a main surface, and there are provided a first plate member in which said projection and the pad provided on the surface opposite to said main surface are electrically connected, a second plate member arranged on the side of a surface forming said pad of said first plate member and in which said pad and a wire formed on said second plate member are electrically connected, and a third plate member arranged between said first plate member and said second plate member, formed by as material having a Young's modulus of 60 GPa or more and having a thickness of 100 μm or more.
 17. A method of manufacturing a semiconductor apparatus as claimed in claim 16, further comprising an elastomer provided between the second plate member and the third plate member.
 18. A method of manufacturing a semiconductor apparatus as claimed in claim 16, wherein said second plate member is a printed circuit board. 